HD8806 WS2818 Pixel LED Strips

How does it work?

It adopts the optimized signal reshaping circuit for signal waveform formation and thus no distortion in message waveform occurs.

It has a built-in reset and reset power-on circuits.

There are grey standard of 256 layers, each of the pixels is a refresh rate of up to 2KHz / s.

Both tasks are performed through a continuous signal line: serial cascade, data collection, and decoding.

Constant propagation of the signal Break-point and loss of any pixel shall not impact the complete show effect.

No other circuits are needed for any two transmission stations which are shorter than 5 meters.

The ripple is not fewer than 1024 pixels, while the refresh rate is 30fps.

It downloads data at 800Kbps rate.

Quality is strong cost-effectiveness of Great performance.

HD8806/WS2818 is a 3-channel the LED driver control circuit that involves the automated lock of smart port data and the amplification of signal reshaping circuits.

It includes a precision internal oscillator and a constant current control programmable 12V voltage that produces a very consistent color effect.

In signal breakpoint continuous transmission, WS2818 has powerful features.

Dual signal transmission takes place, and these signals operate together without interaction.

The customer will choose the first DIN / BIN chip.

Signal input pin and cascade follow-up chips must immediately define a first chip output and do not impact the effect on the whole device.

Single-line contact protocol is followed for HD8806/WS2818 to Return to Zero.

The DIN port is reset after the chip is operated.

The first chip gathers initial 24-bit data, then transfers the data to the internal data latch and the rest to the controller which reshapes the internal amplification circuit signal.

It is sent by the DO port to the next cascade pixel.

Upon transferring both images, the data raises by 24bit.

Because HD8806/WS2818 is self-reshaping, the pixel cascade numbers are not restricted to signal transmission but to signal transmission rates.

The control data is 24-bit greater than the DIN input to guarantee that the control signal receives information.

The internal lock generates different service cycles that control signals dependent on the obtained 24bit data in the OUTR, OUTG, OUTB port.

When the DIN port enters a reset signal, every synchronous chip sends the received data in each line.

After the reset signal has stopped, it can collect fresh data again.

The control signal of the current reset signal is provided to the unaltered OUTR, OUTG, OUTB lock.

After a low point, the chip exports PWM data to OUTR, OUTG, OUTB pins.

The reset voltage signal maintains more than 300us duration.